1. Field of the Invention
The present invention generally relates to logic stages, and, more particularly, to an interlocked restore circuit to ensure sufficient overlap of pulses traveling along different paths to a logic circuit.
2. Description of the Related Art
Clocks are needed in logic arrays to decide when an element that contains a binary logic state, either zero or one, should be updated. In a synchronous system, the signals that are written into state elements must be valid when the clock edge occurs. A signal is valid if it is stable (i.e., not changing) and the value will not change again until the input changes.
One factor to be considered in designing logic circuits is clock skew. Clock skew is the difference in absolute time between when two logic elements see a clock edge. Clock skew arises because the clock signal will often use two different paths, with slightly different delays, to reach two different state elements. These delays may result from factors such as different resistor/capacitor (RC) values along the path.
Therefore, pulsed signals traveling along different paths with different delays can arrive at a logic block without sufficient overlap to produce the correct evaluation. To avoid incorrect operation, the clock period is typically increased to allow for the maximum clock skew as well as the clock set-up and hold time.
In an asynchronous system, however, merely increasing the clock period will not solve the problem. One solution is to wait for a period that is several times longer than the set-up time. Besides slowing the system response time, an additional drawback is that there is still a possibility of insufficient overlap at the input to the logic block to produce a correct result.
In light of the foregoing, there exists a need for an asynchronous logic circuit arrangement and method that provides for sufficient overlap of pulses at a logic circuit regardless of the pulse path.